1. Technical Field
This disclosure relates to integrated circuit design and more specifically to modeling of interconnect wiring in a design.
2. Description of the Related Art
In modern integrated circuit design, a single integrated circuit may include numerous functional units, each of which may be designed to perform a specific function. Each functional unit may be designed in accordance with various design styles dependent upon circuitry included within a given functional unit. For example, a functional unit that includes analog circuitry may be designed using schematics capture, hand-crafted mask design, and circuit simulation. Other functional units may be designed by describing the behavior of digital functions using a hardware description language, such as, e.g., Verilog or VHDL.
When designing a functional unit using a hardware description language, the design of the functional unit may go through various operations before the design is ready for manufacture. For example, logical tests may be performed on the hardware description language to ensure the logical operation of the functional unit is correct. Once the logical operation has been verified, the hardware description language may be translated into a collection of predefined logic gates (commonly referred to as “standard cells”) through a process called “synthesis.”
Once synthesis is complete, the physical placement, orientation, and interconnection of the standard cells may then be performed. Various techniques and algorithms, such as, e.g., simulated annealing, may be employed to determine a location for a given standard cell of the collection of standard cells used to implement the desired logic functions of the functional unit. Once a location has been determined for each standard cell, the interconnection (or “routing”) between the various standard cells may then be performed. Collectively, this process is commonly referred to as “place and route.” Following place and route, additional testing and verification steps may be performed before artworks, i.e., photo masks for the semiconductor manufacturing process, are generated.